This invention relates generally to the field of manufacturing of electronic devices, such as semiconductors or printed circuit boards, and more particularly to routing of a channel in such an electronic device.
Routing has been used extensively mainly in the layout of integrated circuits and printed circuit boards in the prior art. A channel router is designed to route nets that interconnect terminals on two opposite sides of a rectangular region called the channel. Most of the channel routers assume that only two layers are available for interconnection and that the components of routed nets is horizontal and vertical segments. In such prior art routers segments in a specific directionxe2x80x94for example horizontalxe2x80x94are run on one layer and segments in the other direction are run on the other layer.
Terminals are placed at regular intervals and identify the columns of the channel. Horizontal segments are placed so that design rules are not violated. These constraints also identify the rows of the channel. When a net is broken into two or more horizontal segment occupying different rows a technique called xe2x80x9cdogleggingxe2x80x9d is used in the prior art. Doglegging is effective to reduce the number of rows of the channel but it requires additional vias. One example for such a channel router is given in James Reed, Alberto Sangiovanni-Vincentelli, xe2x80x9cA new symbolic router: YACR2xe2x80x9d, IEEE Transactions on Computer-Aided Design, Vol. CAD-4, No. 3, 1985, pp. 208-219.
A channel router must take into consideration vertical constraints. A vertical constraint is a constraint that exists when two nets each have a terminal in the same column. All the vertical constraints that exist for a given channel are usually modeled in a vertical constraint graph (VCG): A VCG is a graph whose nodes represent nets and whose edges represent vertical constraints.
From Bryan Preas, xe2x80x9cChannel Routing with non-terminal Doglegsxe2x80x9d, Proc. The European Design Automation Conference, Glasgow, Scotland, 1990, pp. 451-458, a channel router is known for resolving cyclic vertical constraints. This guarantees the completion of the required interconnections in the channel. The algorithm of this router resolves cyclic constraints by adding non-terminal doglegs to enough wire segments to break all of the constraint cycles. The altered wire segments and the resulting acyclic constraint graph are used as input to an ordinary constraint-based channel router.
The goal of a channel router is to complete the interconnections in a minimum area. Also the number of through vias and lengths of nets are important to evaluate the quality of the routing. The better the quality of the routing the better are the resulting characteristics of the electronic device in terms of power dissipation, operational speed, compactness of design andxe2x80x94in the case of semiconductorsxe2x80x94the amount of precious silicon floor space required.
Therefore this invention seeks to provide an improved method for manufacturing an electronic device as well as an improved method for optimizing a routing of a channel by means of a program as well as an enhanced electronic device having a channel.
The underlying problem of the invention is solved basically by applying the features laid down in the independent claims. The invention is particularly advantageous in that it allows the design of an electronic device that has a maximum local density in its channel which is greater than the number of rows in the channel. This feature can not be realized by any of the prior art channel routers. This allows more efficient utilization of a channel region and a denser wiring structure. Thereby the overall length of the nets is reduced as well as the size of the channel.
These advantages can be crucial for the performance of an electronic device produced according to a manufacturing method of the invention. The shrinkage of the channel region allows a more compact design of the device and to integrate more functionalities within the same space. Also because of the shorter wire length time delays due to signal propagation over the channel are reduced so that the overall operational speed of the electronic device is increased.
For clocked electronic devices this particular advantage of the invention allows to increase the clock frequency. As a further advantage the invention allows also to reduce the power dissipation of an electronic device by optimization of the channel routing. If the routing length of the channel is reduced according to a method for optimizing of the invention this typically results in reduced power dissipation due to the shortened wire length.
According to a preferred embodiment of the invention the row and column segments do not have to be straight lines but can have any curved shape. The routing method of the invention has to advantage to be able to process also such arbitrarily shaped routes.